As the density of active device elements in an Integrated Circuit (IC) increases, so does the importance for electrically isolating adjacent elements in the same substrate. One method for isolating active elements is to provide field isolation regions between adjacent active elements and to provide doped regions within these isolation regions to act as parasitic channel stopping elements. These doped regions eliminate the undesirable conduction due to inversion under the field isolation when lightly doped substrates are used. A process for providing such doped field isolation regions which are also self-aligned to preselected subsequently fabricated active regions is disclosed in U.S. Pat. No. 4,144,101, issued on Mar. 13, 1979 to V. L. Rideout and assigned to the same assignee as the present application.
CMOS circuits use both N channel and P channel devices in the same IC substrate. Conventional processing techniques for making such structures include the formation of single wells or dual wells in preselected portions of a substrate in which individual MOS devices are to be built. U.S. Pat. No. 4,244,752, issued on Jan. 13, 1981 to Henderson, Sr. et al, discloses a process for making CMOS IC's having P-channel and N-channel devices in a P type substrate. A dual dielectric layer of silicon dioxide and silicon nitride is used as a first mask on the surface of the substrate to define the position of the subsequently formed field isolation regions which in turn define the location of the active device regions on the structure. Once the location of the active regions is defined, a second mask is used to form through ion implantation N type well regions for the P channel devices. Using the silicon dioxide-silicon nitride structure as an ion implantation mask the field isolation regions are doped with a P type dopant and subsequently a silicon dioxide layer is grown in these regions for field isolation purposes.
In U.S. Pat. No. 4,385,947, issued on May 31, 1983 to Halfacre et al there is disclosed a method for fabricating CMOS devices in a P type substrate with a single guard ring using local oxidation. The method includes forming a masking layer on a P type silicon substrate having a thin layer of silicon dioxide on it. An opening is formed in the masking layer and the underlying silicon dioxide layer is in a preselected position for the formation of an N-well region. An N dopant is then diffused to form the N-well region. A second masking layer is then formed from an oxide inhibiting material, such as silicon nitride, and patterned to define the position in which the CMOS active regions are to be formed. This layer is then removed from all but location reserved for the active regions. A third masking layer, which may be made from a photoresist material is formed over the structure and patterned to expose the regions preselected for guard ring regions. These regions are then formed through implantation with a P type dopant material. The third masking layer is then removed. The substrate is exposed to an oxidizing atmosphere to grow field oxide on the substrate except on the portions covered by the Si.sub.3 N.sub.4.